1. Field of the Invention
The present invention relates to a variable gain circuit used for a wireless communication apparatus including a mobile terminal.
2. Description of Related Art
A prior art of a variable gain circuit is shown in FIG. 23. This variable gain circuit is provided with a first amplifier 10 of voltage input current output type having high gain and low noise characteristics, and a second amplifier 20 of voltage input current output type having low gain and low distortion characteristics. A gain of the first amplifier 10 is controlled by a first gain control signal 11. Meanwhile, a gain of the second amplifier 20 is controlled by a second gain control signal 21.
The first and the second amplifiers 10 and 20 are connected in parallel with each other. More specifically, an input of the first amplifier 10 and an input of the second amplifier 20 are coupled with each other. A voltage input signal is thereby supplied in common to the first and the second amplifiers 10 and 20. An output of the first amplifier 10 and an output of the second amplifier 20 are also coupled with each other. Thereby, a current output signal of the first amplifier 10 and a current output signal of the second amplifier 20 are additionally combined.
A more specific configuration of the first and the second amplifiers 10 and 20 in FIG. 23 will be shown in FIG. 24. As shown in FIG. 24, the first amplifier 10 is composed of a fixed gain amplifier 10a of voltage input current output type having high gain and low noise characteristics, and a shunt circuit 10b for shunting an output current of the fixed gain amplifier 10a to two current output terminals 10c and 10d at a shunt ratio according to the first gain control signal 11. Meanwhile, the second amplifier 20 is composed of a fixed gain amplifier 20a of voltage input current output type having low gain and low distortion characteristics, and a shunt circuit 20b for shunting an output current of the fixed gain amplifier 20a to two current output terminals 20c and 20d at a shunt ratio according to the second gain control signal 21.
Here, an input terminal of the first fixed gain amplifier 10a and an input terminal of the second fixed gain amplifier 20a form input terminals of the first and the second amplifiers 10 and 20, respectively, and one current output terminals 10c of the first shunt circuit 10b and one the current output terminal 20c of the second shunt circuit 20b form output terminals of the first and the second amplifiers 10 and 20, respectively.
For example, irrespective of a level change of an input signal, this variable gain circuit controls the gains of the first and the second amplifiers 10 and 20 using the first and the second gain control signals 11 and 21 so that an output signal level thereof may become constant. Specifically, when the level of the input signal is low, a combined gain of the first and the second amplifiers 10 and 20 is increased, whereas when the level of the input signal is high, the combined gain of the first and the second amplifiers 10 and 20 is decreased, so that the output signal level is kept constant.
As described above, in order to change the combined gain of the first and the second amplifiers 10 and 20 according to the level of the input signal, it is required to change respective gain contribution factors of the first and the second amplifiers 10 and 20 by the first and the second gain control signals 11 and 21.
When the first and the second amplifiers 10 and 20 are composed like FIG. 24, it is possible to change the respective gain contribution factors of the first and the second amplifiers 10 and 20 to the output of the variable gain circuit by changing the shunt ratio between the shunt circuits 10b and 20b. In other words, when the current fed through the current output terminal 10c for the first amplifier 10 is increased and the current fed through the current output terminal 20c for the second amplifier 20 is decreased, the gain contribution factor of the first amplifier 10 will be increased, and the gain contribution factor of the second amplifier 20 will be decreased. On the contrary, when the current fed through the current output terminal 10c for the first amplifier 10 is decreased and the current fed through the current output terminal 20c for the second amplifier 20 is increased, the gain contribution factor of the first amplifier 10 will be decreased, and the gain contribution factor of the second amplifier 20 will be increased.
As described above, when the variable gain circuit is composed so that the gain thereof may be smoothly changed from a low gain to a high gain by changing the respective gain contribution factors of the first and the second amplifiers 10 and 20 by the first and the second gain control signals 11 and 21, the variable gain circuit with wide dynamic range, which has low noise characteristics at the high gain, and has low distortion characteristics at the low gain can be achieved.
A still more concrete example of a circuit configuration of the variable gain circuit shown in FIG. 23 is shown in FIG. 25. This variable gain circuit has a differential pair 1 and a differential pair 2.
The differential pair 1 composes an amplifier with high gain and low noise. A transistor Q1 and a transistor Q2 are coupled at emitters with each other via a resistor R1, and current sources 111 and 112 are connected to respective emitters.
The differential pair 2 composes an amplifier with low gain and low distortion. A transistor Q3 and a transistor Q4 are coupled at emitters with each other via a resistor R2, and current sources 121 and 122 are connected to respective emitters.
The differential pairs 1 and 2 are then coupled at input terminals with each other. Specifically, a base of the transistor Q1 and a base of the transistor Q3 are coupled with each other, resulting in a differential input Vin1. Meanwhile, a base of the transistor Q2 and a base of the transistor Q4 are coupled with each other, resulting in a differential input Vin2.
Moreover, output terminals of the differential pairs 1 and 2 are coupled with each other. Specifically, emitters of transistors Q5 and Q6 are connected to each other and are connected to a collector of the transistor Q3. Emitters of transistors Q7 and Q8 are coupled with each other and are connected to a collector of the transistor Q1. Emitters of transistors Q9 and Q10 are coupled with each other and are connected to a collector of the transistor Q2. Emitters of transistors Q11 and Q12 are coupled with each other and are connected to a collector of the transistor Q4. Collectors of the transistors Q6 and Q7 are coupled with each other. Collectors of the transistors Q10 and Q11 are coupled with each other. Collector of the transistors Q5, Q8, Q9, and Q12 are connected to a power supply Vcc via resistors, respectively.
In the foregoing configuration, as the output of the variable gain circuit, a collector current Iout1 is derived from a node between the collectors of the transistors Q6 and Q7, and a collector current Iout2 is derived from a node between the collectors of the transistors Q10 and Q11.
Additionally, bases of the transistors Q7 and Q10 are coupled with a positive electrode of a first gain control voltage (gain control signal) Vgca1, and bases of the transistors Q8 and Q9 are coupled with a negative electrode of the first gain control voltage Vgca1. Meanwhile, bases of the transistors Q6 and Q11 are coupled with a positive electrode of a second gain control voltage (gain control signal) Vgca2, and bases of the transistors Q5 and Q12 are coupled with a negative electrode of the second gain control voltage Vgca2.
Next, a gain control method in this variable gain circuit will be described. A collector current of the transistor Q1 shunts to the transistor Q7 and the transistor Q8 according to the gain control voltage Vgca1. For that reason, the transistor Q7 and the transistor Q8 form a linearity current shunt circuit controllable by the gain control voltage Vgca1. Similarly, a collector current of the transistor Q2 shunts to the transistor Q9 and the transistor Q10 by the gain control voltage Vgca1. For that reason, the transistor Q9 and the transistor Q10 form a linearity current shunt circuit controllable according to the gain control voltage Vgca1.
Hence, a current ratio between a pair of the collector currents of the transistor Q7 and the transistor Q10 whose bases are coupled with a positive electrode side of the gain control voltage Vgca1, and a pair of the collector currents of the transistor Q8 and the transistor Q9 whose bases are coupled with a negative electrode side thereof can be controlled according to the gain control voltage Vgca1.
Meanwhile, a collector current of the transistor Q3 shunts to the transistor Q5 and the transistor Q6 according to the gain control voltage Vgca2. For that reason, the transistor Q5 and the transistor Q6 form a linearity current shunt circuit controllable by the gain control voltage Vgca2. Similarly, a collector current of the transistor Q4 shunts to the transistor Q11 and the transistor Q12 according to the gain control voltage Vgca2. For that reason, the transistor Q11 and the transistor Q12 form a linearity current shunt circuit controllable by the gain control voltage Vgca2.
Hence, a current ratio between a pair of the collector currents of the transistor Q6 and the transistor Q11 whose bases are coupled with a positive electrode side of the gain control voltage Vgca2, and a pair of the collector currents of the transistor Q5 and the transistor Q12 whose bases are coupled with a negative electrode side thereof can be controlled according to the gain control voltage Vgca2.
Assuming that a sum of the collector currents derived by coupling respective collectors of the transistors Q6 and Q7 with each other is Iout1, and a sum of the collector currents derived by coupling respective collectors of the transistors Q10 and Q11 with each other is Iout2, it is understood that the current Iout1 and the current Iout2 results in a differential current from the aforementioned description.
The currents flowing through the transistors Q1 and Q2 are then shunted by the transistors Q7, Q8, Q9, and Q10 by changing the gain control voltage Vgca1 as follows, and the currents flowing through the transistors Q3 and Q4 are shunted by the transistors Q5, Q6, Q11, and Q12 by changing the gain control voltage Vgca2 as follows.
In other words, in order to prevent degradation of a noise figure (Noise Figure) in a low input level, the currents flowing through the transistors Q1, Q2, Q3, and Q4 are shunted so that the collector current of the differential pair 1 composing the amplifier with high gain and low noise may be a main current of the output currents Iout1 and Iout2. Additionally, in order to prevent generation of the distortion in a high input level, the currents flowing through the transistors Q1, Q2, Q3, and Q4 are shunted so that the collector current of the differential pair 2 composing the amplifier with low gain and low distortion may be the main current of the output currents Iout1 and Iout2. When the shunted currents are then summed to derive the output currents Iout1 and Iout2, a total gain of the variable gain circuit can be changed smoothly by adjusting the shunt ratio.    [Patent Document 1] Domestic Announcement No. 2002-510888